Product Bulletin
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AR5002AP-2X Solution Highlights
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Supports two
wireless networks, IEEE 802.11a and 802.11b/g, concurrently
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Connects with any
802.11wireless client
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Uses digital CMOS
technology exclusively, minimizing power consumption and cost while
maximizing reliability
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Highly integrated
3-chip set provides unprecedented level of integration, reducing the
chip count for a complete dual-band access point or router from nine
chips to three
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2.4/5 GHz dual band
Radio-on-a-Chip (RoC)
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2.4 GHz
Radio-on-a-Chip
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Wireless
System-on-a-Chip (WiSoC), including integrated 32-bit MIPS
R4000-class processor with dual multiprotocol MAC/baseband
processing engines that support both RoCs
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Super AG® mode delivers up to 108 Mbps raw data rate with typical end user
throughput exceeding 60 Mbps
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Hardware encryption
support for the Wi-Fi Protected Access (WPA) and IEEE 802.11i
security specifications provides Advanced Encryption Standard (AES),
Temporal Key Integrity Protocol (TKIP) and WEP without performance
degradation
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Wireless Multimedia Enhancements Quality of Service
support (QoS)
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Extended tuning
range (2.300-2.500 & 4.900-5.850 GHz) for worldwide use
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Dynamic Frequency
Selection/Transmit Power Control (DPS/TPC) for international
operation
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Support for draft
IEEE 802.11e, h and i standards
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Enhanced third
generation performance, transmission range and reliability
The chipset
includes:
AR5112 Dual band
Radio-on-a-Chip (RoC) for 2.4/5 GHz WLAN
- All CMOS dual band radio chip
- Dynamic IF Dual Conversion architecture provides super-heterodyne
performance at Zero IF prices
- Operates from 2.300 - 2.500 GHz and 4.900 - 5.850 GHz
- Integrated third-generation power amplifier (PA) and low-noise
amplifier (LNA)
- External PA and/or LNA can be used for special applications
- Enhancements to the transmit and receive chains
- Eliminates all IF filters and most RF filters; no external
voltage-controlled oscillators (VCOs) or surface acoustic wave (SAW)
filters needed
AR2112
Radio-on-a-Chip for 2.4 GHz WLAN
- Support for IEEE 802.11b, 802.11g
- Operates from 2.300 - 2.500 GHz
- Advanced wide band receiver with best path sequencer for better
range and multipath resistance than conventional equalizer-based
designs
AR5312 Wireless
System-on-a-Chip
- Integrated 32-bit MIPS R4000-class processor
- Two wireless MAC and baseband processing engines support
concurrent operations
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Super AG® mode includes dynamic 108 Mbps capability, real-time
hardware data compression, dynamic transmit optimization and
standards-compliant bursting
- Two 10/100 Ethernet MACs, high speed UART, 16-bit configurable
local bus
- Integrated analog-to-digital and digital-to-analog converters
- SDRAM and FLASH memory Interface
- Low power operational and sleep modes
AR5002AP-2X WLAN System Architecture

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AR5002AP-2X Specifications |
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Frequency Band |
4.900 to 5.850 GHz and 2.300 to 2.500 GHz |
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Network Standard |
802.11a, 802.11b, 802.11g |
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Modulation Technology |
OFDM with BPSK,
QPSK, 16 QAM, 64 QAM; |
|
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DBPSK, DQPSK, CCK |
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FEC Coding Rates |
1/2, 1/3, 3/4 |
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|
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Hardware Encryption |
AES, TKIP, WEP |
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|
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Quality of Service |
802.11e draft |
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Media Access Technique |
CSMA/CA |
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Host Interface |
|
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Communication Interface |
Two MIIs, High Speed UART, local bus |
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Peripheral Interface |
GPIOs, LEDs |
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Memory Interface |
FLASH, SDRAM |
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|
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Supported Data Rates |
|
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IEEE 802.11a, 802.11b, 802.11g Standard Mode |
1-54 Mbps |
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Atheros Super A Mode |
|
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Atheros Super G Mode |
|
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Atheros Super A/G Mode |
1 - 108 Mbps |
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|
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Chip Specifications |
AR2112 |
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Operating Voltage |
2.5V +/-5% 3.3V +/-10% |
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|
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Package Dimensions |
9mm x 9mm |
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Packaging |
64 Leadless Plastic Chip Carrier |
* Theoretical wireless link rate based
on applicable IEEE 802.11 standards. Actual user
throughput will be lower than the theoretical link rate
and will vary, as network conditions and environmental
factors can lower actual throughput rate. |